(1) Field of the Invention
The present invention relates to a method for fabricating a semiconductor device, and more particularly to a method for fabricating a semiconductor device in which a chemical-mechanical polishing process (hereinafter referred to as a "CMP process") is applied to planarization of interlayer insulation films in a multi-layer interconnection structure.
(2) Description of the Related Art
In recent years, along with advances in higher integration in semiconductor devices, an interconnection structure is becoming more complex requiring a multi-layer interconnection structure. In such a multi-layer interconnection structure, since the interconnection layers and insulation layers are stacked one over another, if the planarized state of a surface of the insulation film is not satisfactory, there occurs a breakage in an overlying interconnection layer so that there is a need for the surface of the insulation film to be planar.
A conventional technology for planarization is disclosed, for example, in Japanese Patent Application Kokai Publication No. Hei 3-280539. The structure fabricated according to this conventional technology is shown in FIG. 1A. In this structure, to a semiconductor substrate 501, a radio frequency bias is applied using an electron cyclotron resonance (ECR) plasma CVD process to form an interlayer insulation film 507 whose buried state at interconnects having level differences is excellent. In the drawings, the reference numeral 502 denotes aluminum interconnections, and 503 denotes gate elements.
Another conventional technology is disclosed in Japanese Patent Application Kokai Publication No. Hei 4-192522, which relates to an improvement over the technology disclosed in Japanese Patent Application Kokai Publication No. Hei 3-280539. As shown in FIGS. 1B and 1C, the method disclosed is one in which first an organic film 514 is applied on an interlayer insulation film 507 formed by the ECR CVD process, and a surface of the interlayer insulation film is further planarized by etching back.
In the first conventional technology described above, in which the ECR plasma CVD process is utilized for directly planarizing the insulation film and in which the insulation film is processed only in the ECR plasma CVD process step, it is difficult to attain a high degree of planarization because, although the buried state of interconnects is excellent in sub-micron level fine pattern regions, the thickness of the insulation layer may increase in an interconnection region where the width thereof is wider than about 4 .mu.m, or a horn-like protrusion may develop on an insulation film surface above an interconnection where the width thereof is narrower than about 2 .mu.m.
In the above described second conventional technology in which the organic film is utilized and is then etched back, although the occurrence of the horn-like protrusion can be prevented and the planarization is improved as compared with that in the first described conventional technology, there are problems in that the planarization of the entire surface of the semiconductor substrate is difficult unless the surface of the organic film formed by the spin coating method is planar. If the extent of planarization is in this way, there will be a problem in that, where the multiplication of layers is further advanced, it will be difficult to enlarge manufacturing tolerances in processes such as a fine precision process in a photolithography process.